
# create_clock -period 40.000 -name clk_in -waveform {0.000 20.000} [get_ports clk_in]
#create_clock -name axi_dynclk_0_PXL_CLK_O -period 6.06 [get_ports SerialClk]
#create_clock -name PXL_CLK_O -period 6.06 [get_ports SerialClk]

#create_clock -period 6.06 axi_dynclk_0_PXL_CLK_O
#create_generated_clock  -name vid_io_out_clk   -source [get_ports axi_dynclk_0_PXL_CLK_O]
#create_generated_clock  -name clk              -source [get_ports axi_dynclk_0_PXL_CLK_O]
#create_generated_clock  -name PixelClk         -source [get_ports axi_dynclk_0_PXL_CLK_O]
    
#set_clock_groups -physically_exclusive   -group {axi_dynclk_0_PXL_CLK_O}   -group {clk}  -group {PixelClk}

# set_property IOSTANDARD LVCMOS33 [get_ports clk_in]
# set_property PACKAGE_PIN N18 [get_ports clk_in]


set_property PACKAGE_PIN M14 [get_ports GPIO_0_0_tri_io[0]]
set_property PACKAGE_PIN M15 [get_ports GPIO_0_0_tri_io[1]]
set_property PACKAGE_PIN N15 [get_ports GPIO_0_0_tri_io[2]]
set_property IOSTANDARD LVCMOS33 [get_ports GPIO_0_0_tri_io[*]]

#----------------------------------------------------------------------------
#CAN_0
#----------------------------------------------------------------------------
# set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_rx]
# set_property PACKAGE_PIN P20 [get_ports CAN_0_rx]

# set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_tx]
# set_property PACKAGE_PIN P19 [get_ports CAN_0_tx]

#----------------------------------------------------------------------------
#USB
#----------------------------------------------------------------------------
# set_property IOSTANDARD LVCMOS33 [get_ports usb_ref_clk]
# set_property PACKAGE_PIN T19 [get_ports usb_ref_clk]

# set_property IOSTANDARD LVCMOS33 [get_ports usb_rst]
# set_property PACKAGE_PIN V16 [get_ports usb_rst]


#----------------------------------------------------------------------------
#device_addr
#----------------------------------------------------------------------------
# set_property IOSTANDARD LVCMOS33 [get_ports {device_addr[5]}]
# set_property PACKAGE_PIN K17 [get_ports {device_addr[5]}]

# set_property IOSTANDARD LVCMOS33 [get_ports {device_addr[4]}]
# set_property PACKAGE_PIN K16 [get_ports {device_addr[4]}]

# set_property IOSTANDARD LVCMOS33 [get_ports {device_addr[3]}]
# set_property PACKAGE_PIN L17 [get_ports {device_addr[3]}]

# set_property IOSTANDARD LVCMOS33 [get_ports {device_addr[2]}]
# set_property PACKAGE_PIN M15 [get_ports {device_addr[2]}]

# set_property IOSTANDARD LVCMOS33 [get_ports {device_addr[1]}]
# set_property PACKAGE_PIN L16 [get_ports {device_addr[1]}]

# set_property IOSTANDARD LVCMOS33 [get_ports {device_addr[0]}]
# set_property PACKAGE_PIN M14 [get_ports {device_addr[0]}]


#----------------------------------------------------------------------------
#485
#----------------------------------------------------------------------------
# set_property IOSTANDARD LVCMOS33 [get_ports rs485_ctrl]
# set_property PACKAGE_PIN J15 [get_ports rs485_ctrl]

# set_property IOSTANDARD LVCMOS33 [get_ports rs485_tx]
# set_property PACKAGE_PIN H17 [get_ports rs485_tx]

# set_property IOSTANDARD LVCMOS33 [get_ports rs485_rx]
# set_property PACKAGE_PIN H16 [get_ports rs485_rx]


# ----------------------------------------------------------------------------
# UART
# ----------------------------------------------------------------------------
# set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_rxd]
# set_property PACKAGE_PIN P18 [get_ports uart_rtl_rxd]

# set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_txd]
# set_property PACKAGE_PIN N17 [get_ports uart_rtl_txd]

# set_property IOSTANDARD LVCMOS33 [get_ports uart2_rtl_rxd]
# set_property PACKAGE_PIN P18 [get_ports uart2_rtl_rxd]

# set_property IOSTANDARD LVCMOS33 [get_ports uart2_rtl_txd]
# set_property PACKAGE_PIN N17 [get_ports uart2_rtl_txd]


#####################
# set_property IOSTANDARD LVCMOS33 [get_ports test_led]
# set_property PACKAGE_PIN G15 [get_ports test_led]

#-------------------------------------------------------------------------
#----------------------      HDMI     ------------------------------------
#-------------------------------------------------------------------------
# set_property IOSTANDARD TMDS_33 [get_ports TMDS_clk_p]
# set_property IOSTANDARD TMDS_33 [get_ports TMDS_clk_n]
# set_property PACKAGE_PIN U14 [get_ports TMDS_clk_p]
# set_property PACKAGE_PIN U15 [get_ports TMDS_clk_n]

# set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_p[0]}]
# set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_n[0]}]
# set_property PACKAGE_PIN Y16 [get_ports {TMDS_data_p[0]}]
# set_property PACKAGE_PIN Y17 [get_ports {TMDS_data_n[0]}]

# set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_p[1]}]
# set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_n[1]}]
# set_property PACKAGE_PIN P14 [get_ports {TMDS_data_p[1]}]
# set_property PACKAGE_PIN R14 [get_ports {TMDS_data_n[1]}]

# set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_p[2]}]
# set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_n[2]}]
# set_property PACKAGE_PIN T14 [get_ports {TMDS_data_p[2]}]
# set_property PACKAGE_PIN T15 [get_ports {TMDS_data_n[2]}]

# set_property IOSTANDARD LVCMOS33 [get_ports {HDMI_OEN[0]}]
# set_property PACKAGE_PIN W15 [get_ports {HDMI_OEN[0]}]

# set_property PACKAGE_PIN U17 [get_ports {hdmi_hpd_tri_i[0]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_hpd_tri_i[0]}]


# ----------------------------------------------------------------------------
# ADC
# ----------------------------------------------------------------------------
# set_property IOSTANDARD LVCMOS33 [get_ports vauxp0]
# set_property IOSTANDARD LVCMOS33 [get_ports vauxn0]

# set_property IOSTANDARD LVCMOS33 [get_ports vauxp1]
# set_property IOSTANDARD LVCMOS33 [get_ports vauxn1]

# set_property IOSTANDARD LVCMOS33 [get_ports vauxp2]
# set_property IOSTANDARD LVCMOS33 [get_ports vauxn2]

# set_property IOSTANDARD LVCMOS33 [get_ports vauxp3]
# set_property IOSTANDARD LVCMOS33 [get_ports vauxn3]

# set_property IOSTANDARD LVCMOS33 [get_ports vauxp4]
# set_property IOSTANDARD LVCMOS33 [get_ports vauxn4]

# set_property IOSTANDARD LVCMOS33 [get_ports vauxp8]
# set_property IOSTANDARD LVCMOS33 [get_ports vauxn8]

# set_property IOSTANDARD LVCMOS33 [get_ports vauxp10]
# set_property IOSTANDARD LVCMOS33 [get_ports vauxn10]

# set_property IOSTANDARD LVCMOS33 [get_ports vauxp12]
# set_property IOSTANDARD LVCMOS33 [get_ports vauxn12]

# set_property PACKAGE_PIN F19 [get_ports vauxp4]     
# set_property PACKAGE_PIN H18 [get_ports vauxn4]

# Vout
# set_property PACKAGE_PIN C20 [get_ports vauxp0]
# set_property PACKAGE_PIN B20 [get_ports vauxn0]
 # temp2
# set_property PACKAGE_PIN M17 [get_ports vauxp10]     
# set_property PACKAGE_PIN M18 [get_ports vauxn10]
 # temp1
# set_property PACKAGE_PIN B19 [get_ports vauxp8]      
# set_property PACKAGE_PIN A20 [get_ports vauxn8]
# temp 3
# set_property PACKAGE_PIN L19 [get_ports vauxp3]      
# set_property PACKAGE_PIN L20 [get_ports vauxn3]
 # IOUT1
# set_property PACKAGE_PIN M19 [get_ports vauxp2]      
# set_property PACKAGE_PIN M20 [get_ports vauxn2]
 # IOUT2
# set_property PACKAGE_PIN E17 [get_ports vauxp1]      
# set_property PACKAGE_PIN D18 [get_ports vauxn1] 
 # temp4
# set_property PACKAGE_PIN F19 [get_ports vauxp12]
# set_property PACKAGE_PIN F20 [get_ports vauxn12]
##  fan_ctrl
# set_property IOSTANDARD LVCMOS33 [get_ports fan_out_ctrl]
# set_property PACKAGE_PIN G14 [get_ports fan_out_ctrl]

# PWM Control
# set_property IOSTANDARD LVCMOS33 [get_ports pwm_sd_1]
# set_property PACKAGE_PIN D20 [get_ports pwm_sd_1]

# set_property IOSTANDARD LVCMOS33 [get_ports pwm_o_1]
# set_property PACKAGE_PIN D19 [get_ports pwm_o_1]

# set_property IOSTANDARD LVCMOS33 [get_ports pwm_sd_2]
# set_property PACKAGE_PIN E19 [get_ports pwm_sd_2]

# set_property IOSTANDARD LVCMOS33 [get_ports pwm_o_2]
# set_property PACKAGE_PIN E18 [get_ports pwm_o_2]

# create_debug_core u_ila_0 ila
# set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
# set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
# set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
# set_property C_DATA_DEPTH 65536 [get_debug_cores u_ila_0]
# set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
# set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
# set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
# set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
# set_property port_width 1 [get_debug_ports u_ila_0/clk]
# connect_debug_port u_ila_0/clk [get_nets [list u_sys_gen/u_motor_drv_ctrl_clk/inst/clk_out1]]
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
# set_property port_width 8 [get_debug_ports u_ila_0/probe0]
# connect_debug_port u_ila_0/probe0 [get_nets [list {u_mrr_bus_slave_top/u_rs485_ctrl/data_rx[0]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_rx[1]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_rx[2]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_rx[3]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_rx[4]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_rx[5]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_rx[6]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_rx[7]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
# set_property port_width 8 [get_debug_ports u_ila_0/probe1]
# connect_debug_port u_ila_0/probe1 [get_nets [list {u_mrr_bus_slave_top/u_rs485_ctrl/data_tx[0]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_tx[1]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_tx[2]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_tx[3]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_tx[4]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_tx[5]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_tx[6]} {u_mrr_bus_slave_top/u_rs485_ctrl/data_tx[7]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
# set_property port_width 1 [get_debug_ports u_ila_0/probe2]
# connect_debug_port u_ila_0/probe2 [get_nets [list u_mrr_bus_slave_top/u_rs485_ctrl/data_rx_end]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
# set_property port_width 1 [get_debug_ports u_ila_0/probe3]
# connect_debug_port u_ila_0/probe3 [get_nets [list u_mrr_bus_slave_top/u_rs485_ctrl/data_tx_en]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
# set_property port_width 1 [get_debug_ports u_ila_0/probe4]
# connect_debug_port u_ila_0/probe4 [get_nets [list u_mrr_bus_slave_top/u_rs485_ctrl/rs485_ctrl]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
# set_property port_width 1 [get_debug_ports u_ila_0/probe5]
# connect_debug_port u_ila_0/probe5 [get_nets [list u_mrr_bus_slave_top/u_rs485_ctrl/rs485_rx]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
# set_property port_width 1 [get_debug_ports u_ila_0/probe6]
# connect_debug_port u_ila_0/probe6 [get_nets [list u_mrr_bus_slave_top/u_rs485_ctrl/rs485_tx]]
# create_debug_port u_ila_0 probe






